1. Field of the Invention
The present invention relates generally to computer devices. More specifically, the present invention relates to automatically compensating the reference clock frequency of a device based on a host clock.
2. Description of the Related Art
Computer architectures have advanced greatly over the years. Lately it is becoming more and more commonplace for chip designers to include external data interfaces, such as Universal Serial Bus (USB) interfaces into their motherboards. These interfaces are known as host controllers. The processor is typically then connected to the other components of the computer system via an input/output (I/O) interconnect system.
There are many different computer I/O interconnect standards available. One of the most popular over the years has been the peripheral component interconnect (PCI) standard. PCI allows the bus to act like a bridge, which isolates a local processor bus from the peripherals, allowing a Central Processing Unit (CPU) of the computer to run must faster.
Recently, a successor to PCI has been popularized, termed PCI Express (or, simply, PCIe). PCIe provides higher performance, increased flexibility and scalability for next-generation systems, while maintaining software compatibility with existing PCI applications. Compared to legacy PCI, the PCI Express protocol is considerably more complex, with three layers—the transaction, data link and physical layers.
In a PCI Express system, a root complex device connects the processor and memory subsystem to the PCI Express switch fabric comprised of one or more switch devices (embodiments are also possible without switches, however). In PCI Express, a point-to-point architecture is used. Similar to a host bridge in a PCI system, the root complex generates transaction requests on behalf of the processor, which is interconnected through a local I/O interconnect. Root complex functionality may be implemented as a discrete device, or may be integrated with the processor. A root complex may contain more than one PCI Express port and multiple switch devices can be connected to ports on the root complex or cascaded.
Some of the host controllers built into chips compatible with PCIe interconnects use the PCIe reference clock as the reference clock for data communications over the external data interfaces. For example, some PCIe-to-USB3.0 host controllers use the PCIe reference clock for transmissions over USB3.0.
A lot of personal computers have non-compliant PCIe clocks, due to overclocking, or the use of a center-spread reference clock instead of a down-spread reference clock to avoid electromagnetic compatibility (EMC) issues. When the clock is used solely for PCIe, these non-compliant clocks have no ill-effect, because the clock signal travels with the data, and thus the receiving device can easily correct for any particular clock problems. Now that these non-compliant PCIe clocks, however, are coupled to USB 3.0 host controllers, this creates some issues.
Unlike PCIe, which transmits a clock signal separate from the data stream, in USB3.0 the attached device has a local reference in addition to recovering a clock signal from the data stream received from the host. In order to ensure that hosts and devices interoperate reliably, the USB3.0 specification only allows for a maximum of a 5600 parts per million (ppm) difference in these clocks. Clock accuracy is typically measured in ppm, and an individual clock's accuracy is typically provided as a range of plus or minus a certain figure from the nominal clock rate of 5 Gbps. The 5600 ppm requirement comes from the fact that a certain amount of disparity between reference clocks can be compensated for by inserting or deleting control characters, known as SKP ordered sets (consisting of two SKP K-Symbols) into or from the data stream. However, the USB3.0 specification only allows for a certain number of these control characters to be inserted or deleted, and a difference of more than 5600 parts per million would require more control characters than are available in the standard.
As described above, the PCIe clock may not simply be different due to overclocking, but also due to the use of a center-spread reference clock. In a center-spread reference clock, the accuracy varies in both the positive direction and the negative direction from the nominal bit rate/ppm. FIG. 1 is a graph illustrating reference clocks of various components. The reference clock for host A 100 is a center-spread reference clock, and as can be seen the clock signal varies from +2500 to −2500 ppm from the nominal bit rate of 5 Gbps. This is in contrast to a down-spread reference clock, the accuracy varies only in the negative direction from a zero point of bit rate/ppm. Here, both host B's reference clock 102 and device's reference clock 104 are shown as down-spread reference clock, both varying the clock signal between 0 and −5000 ppm.
In light of these variances from some PCIe reference clocks and USB3.0 reference clocks, there may be situations where the USB3.0's required maximum difference in clocks of 5600 ppm is violated. Specifically, referring to FIG. 1, the difference between Host A's reference clock 100 and device's reference clock 104 can have a worst case difference of 7500 ppm (depicted at line 106). This despite the fact that both reference clocks individually have no more than a 5000 ppm variance.
Also notably, Host B's reference clock 102, being a down-spread reference clock, will have a maximum difference from the device reference clock 104 of no more than 5000 ppm variance, despite having essentially the same characteristics of Host A's reference clock 100 except for the down-spread aspect.
The grand result of all this is that there are certain situations where an attached USB3.0 device will fail to work with a host controller. There are many such motherboards in the market today.